It should be noted that a serial peripheral interface SPI is an interface that enables the serial i. One bit at a time exchange of data between a number of devices at least one called a master and the others called a slave that operates in fall duplex mode. By full duplex, it is meant that data can be transferred in both directions at the same time.
The SPI is most often employed in systems for communication between the central processing unit CPU and peripheral devices. It is also possible to connect two microprocessors by means of SPI. The invention will now be described in terms of a display controller circuit. It should be noted that although the display controller is described in terms of a flat panel display controller suitable for use in any number and kind of flat panel display monitors, the inventive controller circuit is suitable for any type display deemed appropriate.
Accordingly, the flat panel display described herein includes liquid crystal display LCD type monitors suitable for use with computers and any other device requiring a display. As shown, the display controller includes a processor coupled to a memory device in the form of an SPI-ROM arranged to store both the EDID associated with a display at specific memory locations separate and distinct from those memory locations to store executable instructions and associated data processed by the processor In the described embodiment, the system also includes a number of data ports that provide a transmission link between an external video source such as a computer or PC host and the display controller It should be noted that the DDC standard is a standard that defines a communication channel between a monitor and a display adapter included in a video source to which it is connected.
The monitor uses this channel to convey its identity and capabilities to the display adapter. In a particular implementation, the analog EDID portion spans memory locations - whereas the digital EDID portion spans memory locations - 1 FF but can, of course, be arranged in any manner deemed appropriate. The bridge section is described in more detail below with reference to FIG.
It should be noted, that the bridge section also includes an analog portion During operation, any EDID read request from one of the ports is acted upon by the bridge section by accessing that portion of the ROM that stores the appropriate EDID portion for analog data and portion for digital data.
In this way, even though the power regulator included in the controller is powered off, the bridge section and the ROM still receive sufficient power to provide the necessary EDID during boot-up.
During a power switching transition i. In the described embodiment, the power supply acts to provide power through two branches of cascaded diodes shown in FIG. In the case when the power goes from OFF to ON, the analog section detects the on-board regulator being active and providing power and as a result switches from the active one of the DDC ports that is providing power from the power supply to the now active on-board regulator In this way, the bridge section is always receiving power since any power transition between on-board and off-board power supplies is detected and the appropriate switching action is taken thereby avoiding any power switching glitches.
An auto activity detection circuit described in more detail below located in the analog portion of the bridge section is designed to detect when the power regulator in the controller is powered on or off. In the described embodiment, the detecting is based upon a determination of a current T CLK activity, where T CLK is flat panel controller internal clock.
For example, in the case where the T CLK activity indicates that an on-board crystal clock is active, then the power regulator is determined to be on, whereas, a low T CLK activity indicates that the power regulator is determined to be off. In this way, by seamlessly switching clocks, no glitch or malfunction during the EDID read or flat panel controller operation is likely to occur. During the power-off mode, the power required for the virtual EDID operation is generated by the power supply and provided by way of the cables However, in the power on mode, the current requirement would increase since the controller would be operating at a higher clock frequency.
In this situation, the cable would not be able to sustain the necessary current and, therefore, it is necessary to switch from the cable to the onboard power supply However, there are two conditions that need to be met to enable this switching. In any display product, there is a requirement for a reference clock T LCK that can be generated with internal oscillator, external oscillator or clock source.
The presence of this clock indicates that the chip is in power-on mode. The auto activity detection circuit looks at this the clock signal T CLK and charges a capacitor based on whether it is toggling or low. The capacitor voltage drives an amplifier or inverter and causes a logic state change if it exceeds the threshold voltage of the amplifier or inverter. For example, in the display products, there is generally a microcontroller interface and it is possible to change the register bits once the controller is in power on mode.
As explained above, the T CLK signal itself is sufficient to do the power switching. Since the described controller is I2C compliant, the I2C protocol specification states that any circuit connected to an I2C bus that initiates a data transfer on the bus is considered to be the bus master relegating all other circuits connected to the bus at that time be regarded as bus slaves. In the I2C protocol, when the slave cannot keep up with a master read or write command, the slave holds the bus i.
Therefore, in order to conform to the VESA standard and still remain 12 C compliant, an arbitration circuit provides for execution of both an EDID read request as well as request from other client devices inside controller that require reading the ROM It should be noted that the bridge circuit is a particular implementation of the bridge circuit shown and described in FIG.
As discussed above, in the I2C protocol, when the slave device cannot keep up with a master read or write command, the slave device can hold the bus more like stalling the bus activity from doing any more activity by holding I2C clock one of two wire I2C to low clock stretching. In the described embodiment, the flat panel controller is the slave device and PC host is the master. Therefore, the VESA standard does not provide for the slave device controller to hold the requesting DDC port when data is not ready.
Therefore, in order to maintain compliance with the VESA standard, the arbitration block provides an arbitration service that enables processor to keep up with both an EDID read request rate, as well as request from other circuits inside flat panel controller demanding access to the ROM When the FIFO is almost empty, the processor is flagged indicating that the processor may be required to interrupt other requesting client devices in order to fill the FIFO with additional requested EDID.
When the FIFO is replenished, the processor releases the flag and any other requesting client is permitted access to the ROM The auto activity detection circuit is designed to detect when the power regulator in the controller is powered on or off.
The auto activity detection circuit will charge the capacitor C 1 when the T CLK is toggling and the node N 1 will charge to high voltage causing node N 2 to be high. Alternatively, when the T CLK is zero, the capacitor C 1 is not charging and the high impedance resistor R 2 will pull down the Node N 1 causing node N 2 to be low which makes node N 3 low resulting in the output ACT signal being low indicating that the controller power is off.
The process begins at by a determination if the flat panel controller FPC is powered on. Returning to , if, in the alternative, the controller has been determined to be powered off, then control is passed directly from to where if the DDC state machine is determined to be busy, then control is passed back to , otherwise, the controller state machine is granted access to the ROM at At , a determination is made if other ports are requesting access to the ROM.
If no other ports are requesting access, then the controller services all requests at , otherwise, at the controller services all requests and provides any requesting port access to the ROM. The process begins at by activating an on-board power supply and at disconnecting an off-board power supply arranged to provide power to the memory device when the on-board power supply is activated.
Next at providing power from the on-board power supply to a memory device used to store the EDID and the executable instructions and associated data and at providing power from the on-board power supply to an on-board clock circuit capable of providing a high frequency clock signal. At , providing the high frequency clock signal from the on-board clock circuit to the memory device, and at if a memory read operation was in progress when the on-board power supply was activated, then completing the memory read operation at The process begins at by generating a memory access request by the requesting data port and at , granting access to the memory device by the arbitration circuit.
At , generating a processor memory access request by the processor and at , a determination is made whether or not the data buffer is determined to full. If it is determined that the data buffer is full, then at the processor memory access request is granted, and in any case, at the requesting port continues to read from the buffer.
At , a determination is made whether or not the buffer is almost empty and if it is determined to be almost empty, then at , the requesting port is granted access to the memory, otherwise, the requesting port continues to read data from the buffer. The process begins at by generating an EDID read request by the host device and at passing the EDID read request by way of the requesting port to the memory device.
At , the requested EDID is transferred from the memory device to a data buffer while at , memory access is granted to the processor, and at reading the requested EDID from the buffer in a byte by byte manner; and sending each byte of data through the requesting data port bit by bit to the host device at The process begins at by determining if an on-board power supply is active.
If the on-board power supply is not active, then power is provided to the display controller by an off-board power supply by way of the connector at and at a low power, low frequency clock arranged to provide a low frequency clock signal is turned on thereby preserving power. However, when at , it is determined that the on-board power supply is not active, then at power is supplied to the display controller by the on-board power supply only and at , the low frequency clock is turned off and at , the high frequency clock arranged to provide a high frequency clock signal is turned on.
The process starts at by receiving a reference clock signal at an input node and at generating a first voltage at a first resistor coupled to the input node. At , charging a capacitor coupled to the first resistor, or not, based upon the first voltage and at , reading a capacitor output voltage.
At , a determination is made whether or not the capacitor output voltage is HIGH and if it is determined to be HIGH, then at , the reference clock signal is determined to be active and on the other hand, if the capacitor output voltage is not HIGH, then at , the reference clock signal is determined to be not active.
System includes central processing unit CPU , random access memory RAM , read only memory ROM , one or more peripherals , primary storage devices and , graphics controller , and digital display unit Graphics controller generates image data and a corresponding reference signal, and provides both to digital display unit The image data can be generated, for example, based on pixel data received from CPU or from an external encode not shown.
For example, image data can include video signal data also with a corresponding time reference signal. Although only a few embodiments of the present invention have been described, it should be understood that the present invention may be embodied in many other specific forms without departing from the spirit or the scope of the present invention.
As background, I2C is a low level, slow speed specification of a 2 wire protocol for sending and receiving bytes. For example, only certain byte sequences are legal. It leaves the bit-banging to the video device drivers, e. One source of confusion in DDC documentation is the specification of slave adddresses on the I2C bus.
Leaving aside the implementation of 10 bit I2C bus addresses uncommon , I2C slave addresses are encoded in a single byte. The high order 7 bits are used for the address per se. The low order bit is 0 for a write operation, 1 for a read operation. Wikipedia has several high quality pages on related specifications: They The may be helpful when trying to figure out why DDC communication is not working:.
Docs » Background » References. The following specifications and articles provide backgroud information about the I2C bus.
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